ECE 627Register-transfer-level Digital Systems
- Units
- 0.50
- Level
- Graduate
- Faculty
- Engineering
ECE 627 as listed in the Spring 2024 Graduate Calendar. The main page has the current version, when it runs, and seats.
Syntax, semantics, and usage of the VHDL hardware description language. Modeling concurrency in VHDL, in other hardware description languages, and using other simulation techniques. Modeling, design, and implementation at the register-transfer level. Functional verification techniques. Timing analysis. Introduction to power analysis and optimization. Introduction to faults and testing.
Prerequisites
None listed.
Antirequisites
None listed.
Leads to
No course lists it as a requisite.
Check it elsewhere for Spring 2024
- Graduate Calendar, Spring 2024The archived entry
- Requirements for Spring 2024Waterloo’s requisite checker
- Course outlinesSyllabi from past terms (UW login)
- UW FlowStudent ratings and reviews
- WClassesPast sections back to 2004, and who taught them
Calendar versions
Graduate Calendar
- Spring 2024 (shown here)
- Fall 2024
- Winter 2025
- Spring 2025
- Fall 2025
- Winter 2026
- Spring 2026 requisites changed
- Fall 2026